SVI-806 - 80 COLUMN
===================


The SVI-806 80-column Video Card, Part 1. 
from Gregory S. Vigneault, Toronto, Canada. z180@hotmail.com 

The SVI-806 uses the Motorola MC6845 chip, second-sourced by Hitachi (HD6845). Fortunately, the IBM PC also uses/emulates the 6845 for its CGA video modes, so there's lots of info about how to program this video control IC. Note: CRTC is an acronym for "cathode-ray tube (CRT) controller." 

In the SVI, the 6845 video RAM (2048 bytes) is "shadowed" into high memory, starting at address 0F000h. To enable/disable the video RAM, set/clear bit-0 of i/o port 58h. For example... 

  ld  a,1       ; to set bit-0 
  di            ; interrupts should be disabled! 
  out (58h),a   ; set bit0 to enable 6845 VRAM at 0F000h 
  ...           ; now do [whatever] with memory-mapped VRAM 
  xor a         ; a cheap zero 
  out (58h),a   ; clear bit0 to disable 6845 VRAM 
  ei            ; end of critical section 

While bit-0 of port 58h is set (1), the 80-column card will
*instantaneously* assert the RAMDIS bus signal whenever it detects an access to memory address 0F000h and above. This disables ALL onboard SVI RAM -- so interrupts MUST be disabled, and there MUST be no code or stack above address 0EFFFh while the 6845 video RAM is enabled!! 

Here's how the SVI CP/M CBIOS detects and initializes the 80-column card; Disk BASIC would do something similar... 

; 80-column card initialize (this code not optimized for the Z-80) ;
nit80:  di 
        ld    a,15        ; the 6845 register we want to access 
        out   (50h),a     ; 6845 reg address latch port 
        xor   a           ; cheap zero 
        out   (51h),a     ; 6845 data port 
        ld    b,a         ; for later compare 
        in    a,(51h)     ; read it back (0FFh if not there) 
        cp    b           ; same? 
        jp    nz,not80c   ; if not, 6845 isn't there 
        inc   a 
        jp    nz,presnt   ; if it wasn't 0FFh, all is fine 
not80c:                   ; use VDP if no 6845 detected... 
        ld    hl,crtout   ; address of alternate code 
        ld    (fudge),hl  ; change conout vector in dispatch table 
        ld    a,(IOBYT)   ; now re-assign console to CRT: 
        and   0FCh        ; leave all but CON: 
        or    1           ; force CON: to 40-column card (CRT:) 
        ld    (IOBYT),a   ; so CBIOS calls BASIC ROM for VDP 
        ret 
presnt:                   ; if 6845 was detected... 
        ld    a,0FFh      ; 'cause we need bit-0 set to 1 
        out   (58h),a     ; to enable 6845 VRAM 
        ld    hl,0F000h   ; base of VRAM 
        ld    bc,7FFh     ; init 2k of VRAM 
loop1:  ld    a,0         ; zero 
        ld    (hl),a      ; 00h in VRAM displays blank space 
        inc   hl          ; update VRAM pointer 
        dec   bc          ; byte count-down 
        ld    a,b         ; check for zero 
        or    c 
        jp    nz,loop1    ; loop to zero entire VRAM 
                          ; now initialize the 6845 registers... 
        ld    c,0         ; starting 6845 register 
        ld    hl,crtbl    ; address of data table (see below) 
next:   ld    a,c         ; get reg addr/count 
        cp    10h         ; done loading the 15 registers? 
        jp    z,eint      ; jif so 
        out   (50h),a     ; select 6845 reg 
        ld    a,(hl)      ; get data from table 
        out   (51h),a     ; init the 6845 reg 
        inc   hl          ; update table ptr 
        inc   c           ; update reg count 
        jp    next        ; loop for all registers 
eint: 
        xor   a           ; cheap zero 
        out   (58h),a     ; disable 6845 VRAM 
        ei                ; breathe easy now 
        ret
;
; the following data is to initialize the 6845 registers ; 
crtbl:  db    109     ; R0  - horizontal total register 
        db    80      ; R1  - horiz displayed reg 
        db    89      ; R2  - horiz sync position reg 
        db    12      ; R3  - horiz sync width reg 
        db    31      ; R4  - vertical total reg 
        db    2       ; R5  - vert total adjust reg 
        db    24      ; R6  - vert displayed reg 
        db    26      ; R7  - vert sync position 
        db    0       ; R8  - interlace mode reg 
        db    7       ; R9  - max scan line address reg 
        db    60h     ; R10 - cursor start reg 
        db    7       ; R11 - cursor end register 
        db    0       ; R12 - start addr reg (L) 
        db    0       ; R13 -   "    "    "  (H) 
        db    0       ; R14 - cursor reg (L) 
        db    0       ; R15 -   "     "  (H) 



Note: Before writing into video RAM, the CBIOS translates ASCII codes into "raw" bytes that the 6845 hardware can use: ASCII 20h..7Eh are mapped to 00h..5Eh (for normal video), and 60h..0BEh (reverse video), and graphic symbols 0A0h..0DEh are mapped to 0C0h..0FFh. Code 0BFh is reserved for the cursor. As you can see, the 80-column initialization code fills VRAM with zeros (00h), which causes the 6845 to display all blank spaces (20h) on the CRT. 

Okay, that's all, for now! 

IF I get compelling questions about the SVI-806 (or about other SVI things), I'll write a follow-up article exclusively for Tomas Karlsson's FANTASTIC website! (Go ahead, inspire me!)